Intel® Stratix® 10 Hard Processor System Technical Reference Manual

ID 683222
Date 11/28/2022
Public

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3.6.2. Bringing the Cortex® -A53 MPCore™ out of Reset

When a cold or warm reset is issued to the ARM® Cortex® -A53 MPCore™ Processor, CPU0 is released from reset automatically. CPU1, CPU2 and CPU3 reset signals remain asserted when a cold or warm reset is issued. After CPU0 comes out of reset, you can deassert the other CPU reset signals by clearing the CPUn bits in the MPU Module Reset (mpumodrst) register in the Reset Manager.

A cold reset, resets the entire ARM® Cortex® -A53 MPCore™ , including any debug functionality. A warm reset, resets all of the MPCore™ , except for the debug logic.

Table 39.  Reset Combinations
Reset Type Description
HPS cold reset The ARM® Cortex® -A53 MPCore Processor is held in reset and powered down.
HPS cold reset with active debug Each of the four cores in the ARM® Cortex® -A53 MPCore Processor are held in reset. The L2 cache is held in reset but powered. Debug is enabled.
Individual ARM® v8-A core cold reset with active debug One of the four cores is in held in reset so that it can be powered. The L2 cache and debug are released from reset. This configuration enables external debug over power down for the core that is held in reset.
Individual ARM® v8-A core warm reset with trace enabled and active debug One of the four cores is held in reset and debug is active.