Intel® Stratix® 10 Hard Processor System Technical Reference Manual

ID 683222
Date 11/28/2022
Public

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25.4.1. Debug Access Port

The Debug Access Port (DAP) provides the necessary ports for a host debugger, like the Arm* Development Studio 5* (DS-5*) for Intel® SoC FPGA Edition running on a workstation, to connect to and communicate with the HPS through a JTAG interface. DAP is connected to the host using JTAG. Once this connection has been established, the debugger can access various modules inside the HPS.

There are several sub-components:
  • Serial Wire JTAG Debug Port (SWJ-DP)
  • DAPBUS interconnect
  • DAPBUS async bridge
  • DAPBUS sync bridge
  • JTAG Access Port (JTAG-AP)
  • AXI Access Port (AXI-AP)
  • AHB Access Port (AHB-AP)
  • APB Access Port (APB-AP)
The following figure shows how they are all integrated.
Figure 143. DAP Integration

Once connected, the host can access the DAPB port of the CoreSight components by using the APB-AP.

The debugger can access the system resources with the DAP which supports an AXI-AP port. The AXI-AP supports an AXI master that allows the debugger to access several memory mapped in HPS resources. The AXI-AP master port is connected to the L4 Main Switch.

This connection can be used by the debugger to access the state of an IP block that exists in FPGA.
Note: It is important to remember that all methods of access made by the debugger over an AXI port show up as normal access. There is no way for an IP block to know that an access is being made by the debugger.

A host debugger can access any HPS memory-mapped resource in the system through the DAP system master port. Requests made over the DAP system master port are impacted by reads and writes to peripheral registers.

For more information, refer to the CoreSight Components Technical Reference Manual on the ARM® Infocenter website.