Intel® Stratix® 10 Hard Processor System Technical Reference Manual

ID 683222
Date 11/28/2022
Public

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3.6.1. Enabling Cortex® -A53 MPCore™ Clocks

After the Cortex® -A53 MPCore™ comes out of reset, the mpuclken bit in the mainpllgrp of the Clock Manager is set to 1 by default and the processor clock group is enabled. To disable the processor clock group at any time you can write a 1 to the mpuclken bit of the enr register in privileged mode.

When the processor comes out of reset, the secure internal oscillator is enabled. To use a different source, set the mpu bit in the bypassr register of the mainpllgrp of registers in the Clock Manager. Next, select the source and frequency by programming the mpuclk register in the mainpllgrp of register in the Clock Manager.