Intel® Stratix® 10 Hard Processor System Technical Reference Manual

ID 683222
Date 11/28/2022
Public

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14.4. Intel Stratix 10 Pin MUX Test Considerations

The HPS dedicated I/O pins are chained into the full chip JTAG boundary scan chain.

In some power modes the HPS can be off or disabled. However, the boundary scan chain still includes the HPS dedicated I/O pins, even when the HPS is inactive.

While the boundary scan is taking place, you must ensure that no software is executing in the HPS.

Note: You can only perform boundary scan with the FPGA JTAG. HPS JTAG does not support boundary scan.