Intel® Stratix® 10 Hard Processor System Technical Reference Manual

ID 683222
Date 11/28/2022
Public

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6.2.9.3. SDRAM L3 Firewalls

All data that is routed to the SDRAM scheduler must pass through the firewalls.

The SDRAM L3 firewalls define memory access regions in the SDRAM. Each SDRAM L3 interconnect master has its own memory access regions, independent of the other masters. The following block diagram shows the connectivity of the SDRAM L3 firewalls:

Figure 26. SDRAM L3 Interconnect Firewalls

The firewalls define whether each memory access region is protected or unprotected relative to its master. You can configure the size of each memory region between 64 KB and 128 KB, on 64 KB boundaries. The following table lists the number of available memory access regions for each master.

Table 72.  Memory Access Regions for SDRAM Masters
SDRAM Master Number of Memory Access Regions
MPU 8
I/O coherent masters:
  • FPGA-to-HPS bridge
  • HPS peripheral masters
  • SMMU TCU
7
FPGA-to-SDRAM port 0 4
FPGA-to-SDRAM port 1 4
FPGA-to-SDRAM port 2 4

The SDRAM L3 interconnect regulates access to the hard memory controller with the firewalls, which support secure regions in the SDRAM address space. Accesses to the SDRAM pass through the firewalls and then through the scheduler.