Intel® Stratix® 10 Hard Processor System Technical Reference Manual

ID 683222
Date 11/28/2022
Public

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25.4.9.1. Cross Trigger Interface

The HPS CTI is connected to authentication signals.

Trigger outputs can be masked when the invasive debug enable signal is LOW, to avoid debug tools changing the behavior of the system. If the corresponding bit of todbgensel bit is set to LOW, then the trigger outputs are masked by the dbgen signal. Otherwise, if the corresponding bit of todbgensel bit is set to HIGH, then the trigger outputs ignore the dbgen signal.

Trigger inputs can be masked when the non-invasive debug enable signal is LOW, to avoid debug tools being able to observe the state of the system. If the tinidensel bit is set to LOW, then the trigger outputs are masked by the niden signal. Otherwise, if the tinidensel bit is set to HIGH, then the trigger outputs ignore the niden signal.

In the HPS Cortex-A53 cluster, there are additional CTM available to communicate with other CTIs to control the halt mode of the generic timer.

The HPS debug system contains the following CTIs:
  • CTI—performs cross triggering between the STM, ETF, ETR, and TPIU.
  • FPGA-CTI—exposes the cross-triggering system to the FPGA fabric.
  • CTI-0 and CTI-1—reside in the MPU debug subsystem. Each CTI is associated with a processor and the processor’s ETM.