Intel® Stratix® 10 Hard Processor System Technical Reference Manual

ID 683222
Date 11/28/2022
Public

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8.3.2.1. Handshake Rules

The DMAC uses the DMA handshake rules that are listed, below, when a DMA channel thread is active, that is, not in the Stopped state.

  • drvalid can change from LOW to HIGH on any aclk cycle, but it must only change from HIGH to LOW when drready is HIGH.
  • drtype can only change when either drready is HIGH, or drvalid is LOW.
  • drlast can only change when either drready is HIGH, or drvalid is LOW.
  • davalid can change from LOW to HIGH on any aclk cycle, but it must only change from HIGH to LOW when daready is HIGH.
  • datype can only change when either daready is HIGH, OR davalid is LOW.
Table 84.  DMA Peripheral Interface Signal Definition
Signal Description
drready
Indicates whether the DMAC can accept the information that the peripheral provides on drtype_<x>[1:0]:
  • 0 = DMAC not ready
  • 1 = DMAC ready
Note: If drvalid is HIGH then the DMAC sets drready to HIGH when it accepts the peripheral request.
drvalid
Indicates when the peripheral provides valid control information:
  • 0 = No control information is available
  • 1 = drtype_<x>[1:0] and drlast_<x> contain valid information for the DMAC
Note: The peripheral sets drvalid HIGH when it starts to provide valid control information on drlast and drtype. The state of drvalid, drlast and drtype must remain constant until the DMAC sets drready HIGH.
drtype[1:0]
Indicates the type of acknowledgment, or request, that the peripheral signals:
  • b00 = single level request
  • b01 = burst level request
  • b10 = acknowledging a flush request that the DMAC requested
  • b11 = reserved
drlast
Indicates that the peripheral is sending the last data transfer for the current DMA transfer:
  • 0 = last data request is not in progress
  • 1 = last data request is in progress
Note: The DMAC only uses this signal when drtype_<x>[1:0] is b00 or b01.
daready
Indicates whether the peripheral can accept the information that the DMAC provides on datype_<x>[1:0]:
  • 0 = peripheral not ready
  • 1 = peripheral ready
Note: If davalid is HIGH, the peripheral sets daready HIGH when either it:
  • Accepts a flush request from the DMAC
  • Acknowledges the completion of a DMA transfer
davalid
Indicates when the DMAC provides valid control information:
  • 0 = no control information is available
  • 1 = datype_<x>[1:0] contains valid information for the peripheral
Note: The DMAC sets davalid HIGH when it starts to provide valid control information on datype. The state of davalid and datype remain constant until the peripheral sets daready HIGH.
datype[1:0]
Indicates the type of acknowledgment, or request, that the DMAC signals:
  • b00 = The DMAC has completed the single DMA transfer
  • b01 = The DMAC has completed the burst DMA transfer
  • b10 = DMAC requesting the peripheral to perform a flush request
  • b11 = reserved

For more information, refer to the "Peripheral Request Interface Timing Diagrams" chapter.