Intel® Stratix® 10 Hard Processor System Technical Reference Manual

ID 683222
Date 11/28/2022
Public

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9.3.3. On-Chip RAM Burst Support

The on-chip RAM AXI bus interface supports INCR and WRAP burst types for both reads and writes. The on-chip RAM does not support fixed bursts greater than a length of one beat. If a fixed burst greater than 1 is attempted a SLVERR is returned on the bus.

The on-chip RAM supports the following burst features:
Table 86.  Burst Features
Feature Description
Burst types
  • FIXED—Only the one-beat fixed burst is supported and has a length of 1
  • INCR—1 to 256
  • WRAP—2, 4, 8, or 16
Burst size 1, 2, 4, 8 bytes

For any access lower than 8 bytes, the controller determines which bytes are valid.

Burst lengths 1 to 16 beats
Latency Supports back to back single beat bursts. This applies to reads, writes, and combined reads and writes.
Error response If the fixed burst length is greater than 1, a SLVERR is returned.