Intel® Stratix® 10 Hard Processor System Technical Reference Manual

ID 683222
Date 11/28/2022
Public

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14.3.3.3. FPGA Access MUX Registers

The FPGA access MUX registers (sometimes called "use FPGA" registers) select whether each HPS peripheral uses HPS I/O pins or is routed to the FPGA fabric. Platform Designer determines the values of the FPGA access MUX registers automatically when you configure the HPS component.

You can route most peripherals (except USB and GPIO) to the FPGA. The following FPGA access registers are available:

  • pinmux_emac0_usefpga
  • pinmux_emac1_usefpga
  • pinmux_emac2_usefpga
  • pinmux_i2c0_usefpga
  • pinmux_i2c1_usefpga
  • pinmux_i2c_emac0_usefpga
  • pinmux_i2c_emac1_usefpga
  • pinmux_i2c_emac2_usefpga
  • pinmux_nand_usefpga
  • pinmux_sdmmc_usefpga
  • pinmux_spim0_usefpga
  • pinmux_spim1_usefpga
  • pinmux_spis0_usefpga
  • pinmux_spis1_usefpga
  • pinmux_uart0_usefpga
  • pinmux_uart1_usefpga
  • pinmux_mdio0_usefpga
  • pinmux_mdio1_usefpga
  • pinmux_mdio2_usefpga

At cold reset, the FPGA access registers default to 0, selecting the HPS I/O pins. A warm reset event does not affect these registers.

Note: Although the FPGA access MUX is configured through the control registers, Intel recommends against reconfiguring the FPGA access MUX after I/O configuration is complete.