Intel® Stratix® 10 Hard Processor System Technical Reference Manual

ID 683222
Date 11/28/2022
Public

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4.5.2.1. Coherency Directory

The cache coherency unit uses a directory-based coherency protocol. The CCU has a memory structure that tracks the state of the L2 cache lines.

The coherency directory stores cache line addresses and state information about each address. The directory does not store cache line data. It is not a cache. The coherency directory only contains address and state information that other master agents snoop when making coherent accesses. The directory acts as a snoop-filter and assists the cache coherency controller in locally determining the state of a cache line without sending snoops to the L2 cache.

The directory-based protocol provides lower latency accesses, reduced network bandwidth, reduced snoop traffic for the Cortex® -A53 MPCore™ , and higher peak bandwidth of the system.

When the Cortex® -A53 MPCore™ replaces a cache line, it sends an evict request to the coherency directory for any clean lines it is dropping. The directory no longer tracks those addresses after the eviction request completes.

A module reset clears the CCU coherency directory arrays and all ECC bits. You can also clear the entire CCU coherency directory RAM array through the CCC Directory Invalidation Control and Status Register (agent_ccc0_ccc_directory_inv) at offset 0x30080. When the CCU coherency directory RAM clears, coherent state information is lost and copies of lines held by masters are no longer tracked.
Note: If you trigger an invalidation under register control, Intel recommends that you ensure that there are no outstanding coherent requests. It is also recommended that you invalidate the directory only when you are invalidating the L2 cache as well.