Intel® Stratix® 10 Hard Processor System Technical Reference Manual

ID 683222
Date 11/28/2022
Public

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7.8. Ready Latency Support

The HPS-to-FPGA and FPGA-to-HPS bridges support an optional ready latency feature, which allows your design to run at a higher FMAX. When enabled, this feature adds a pipeline stage to improve the timing performance of the handshake between the HPS and the FPGA fabric.

You can check the bridges' FMAX performance by viewing the fitter report in Intel® Quartus® Prime. Ready latency supports a delay of up to 4 clock cycles. You can enable the delay in Platform Designer.