Intel® Stratix® 10 Hard Processor System Technical Reference Manual

ID 683222
Date 11/28/2022
Public

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Document Table of Contents

25.4.5. CoreSight Trace Memory Controller

The CoreSight Trace Memory Controller (TMC) has three possible configurations:
  • Embedded Trace FIFO (ETF)
  • Embedded Trace Router (ETR)

ETB is not used in this device.

For more information, refer to the CoreSight System Trace Memory Controller Technical Reference Manual on the ARM® Infocenter website.