Intel® Stratix® 10 Hard Processor System Technical Reference Manual

ID 683222
Date 11/28/2022
Public

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17.6.5.2.3. End-to-End Transparent Clock

The end-to-end transparent clock supports the end-to-end delay measurement mechanism between slave clocks and the master clock. The end-to-end transparent clock forwards all messages like normal bridge, router, or repeater. The residence time of a PTP packet is the time taken by the PTP packet from the ingress port to the egress port.

The residence time of a SYNC packet inside the end-to-end transparent clock is updated in the correction field of the associated Follow_Up PTP packet before it is transmitted. Similarly, the residence time of a Delay_Req packet inside the end-to-end transparent clock is updated in the correction field of the associated Delay_Resp PTP packet before it is transmitted. Therefore, the snapshot needs to be taken at both ingress and egress ports only for PTP messages SYNC or Delay_req. You can take the snapshot by setting the snapshot select bits (SNAPTYPSEL) to b'10 in the Timestamp Control (gmacgrp_timestamp_control) register.

The snaptypsel bits, along with bits 15 and 14 in the Timestamp Control register, decide the set of PTP packet types for which a snapshot needs to be taken. The encoding is shown in the table below:

Table 185.  Timestamp Snapshot Dependency on Register Bits X is defined as a "don't care" in the table.
snaptypsel (bits[17:16]) tsmstrena (bit 15) tsevntena (bit 14) PTP Messages
0x0 X 0 SYNC, Follow_Up, Delay_Req, Delay_Resp
0x0 0 1 SYNC
0x0 1 1 Delay_Req
0x1 X 0 SYNC, Follow_Up, Delay_Req, Delay_Resp, Pdelay_Req, Pdelay_Resp, Pdelay_Resp_Follow_Up
0x1 0 1 SYNC, Pdelay_Req, Pdelay_Resp
0x1 1 1 Delay_Req, Pdelay_Req, Pdelay_Resp
0x2 X X SYNC, Delay_Req
0x3 X X Pdelay_Req, Pdelay_Resp