Intel® Stratix® 10 Hard Processor System Technical Reference Manual

ID 683222
Date 11/28/2022
Public

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7.3.1.2. FPGA-to-HPS CCU (ACE-lite*)

  • For all coherent and non-coherent operations, AxDOMAIN[1:0] must be ‘b01 (Inner Shareable).
  • For all burst transactions, AxBURST must be either ‘b01 (INCR) or ‘b10 (WRAP).