Intel® Stratix® 10 Hard Processor System Technical Reference Manual

ID 683222
Date 11/28/2022
Public

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12.5. Reset Signals and Registers

The reset manager uses the following module reset signals to assert reset for the respective modules during different reset domain. Most of these signals are driven internally, and you do not have any control over them. These signals are solely listed to explain the reset manager functionality.
Note: For warm resets, software can set the brgwarmmask registers to prevent the assertion of module reset signals to peripheral modules.
When a module that has been held in reset is ready to start running, software can deassert the respective reset signal by writing to the following appropriate register.
Modules Module Reset Signal Register
FPGA fabric s2f_rst -
s2f_cold_rst -
s2f_watchdog_rst -
Debug domain with CoreSight and Trace dbg_rst_n dbgmodrst.dbg_rst

dbgmodrst.csdap_rst

MPU corereset_n [3:0] mpumodrst.core[3:0]
cpuporreset_n [3:0] coldmodrst.cpupor[3:0]
l2reset_n coldmodrst.l2
DMA dma_rst_n per0modrst.dma
dma_ecc_rst_n per0modrst.dmaocp
dma_periph_if_rst_n [7:0] per0modrst.dmaif[7:0]
SPI Master and Slave spim_rst_n [1:0] per0modrst.spim[1:0]
spis_rst_n [1:0] per0modrst.spis[1:0]
Ethernet MAC emac_rst_n [2:0] per0modrst.emac[2:0]
emac_ecc_rst_n [2:0] per0modrst.emac[2:0]ocp
emac_ptp_rst_n per0modrst.emacptp
USB usb_rst_n [1:0] per0modrst.usb[1:0]
usb_ecc_rst_n [1:0] per0modrst.usb[1:0]ocp
NAND Flash nand_flash_rst_n per0modrst.nand
nand_flash_ecc_rst_n per0modrst.nandocp
SD/MMC sdmmc_rst_n per0modrst.sdmmc
sdmmc_ecc_rst_n per0modrst.sdmmcocp
Watchdog watchdog_rst_n [3:0] per1modrst.watchdog[3:0]
Timer l4sys_timer_rst_n [1:0] per1modrst.l4systimer[1:0]
sp_timer_rst_n [1:0] per1modrst.sptimer[1:0]
I2C i2c_rst_n [4:0] per1modrst.i2c[4:0]
UART uart_rst_n [1:0] per1modrst.uart[1:0]
GPIO gpio_rst_n [1:0] per1modrst.gpio[1:0]
HPS-to-FPGA Bridge s2f_bridge_rst_n brgmodrst.soc2fpga
FPGA-to-HPS Bridge f2s_bridge_rst_n 26 brgmodrst.fpga2soc
Lightweight HPS-to-FPGA Bridge lws2f_bridge_rst_n brgmodrst.lwsoc2fpga
FPGA-to-SDRAM f2s_sdram_bridge_rst_n [2:0] brgmodrst.f2ssdram[2:0]
SDRAM Scheduler ddr_scheduler_rst_n brgmodrst.ddrsch
TAP tap_rst_n tapmodrst.tap
Note: SDM sends a reset command to external flash. You must not connect anything to the reset signal of the external flash. For example, do not connect HPS_COLD_nRESET to the external flash.
For signals and registers, you may see the following naming convention used interchangeably:
  • f2s or f2h (Direction: FPGA to HPS or SoC)
  • s2f or s2f (Direction: HPS to SoC to FPGA)
26 Software must never reset this bridge. This bridge must only be reset by POR/COLD/WARM reset.