Intel® Stratix® 10 Hard Processor System Technical Reference Manual

ID 683222
Date 11/28/2022
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

2.2.6.1.1. Stratix 10 HPS SDRAM Scheduler

The SDRAM scheduler accepts read and write requests from the processor, HPS peripheral masters, and soft logic in the FPGA (through the FPGA-to-SDRAM interface). It is programmed with memory timings, allowing it to optimize memory accesses.