Intel® Stratix® 10 Hard Processor System Technical Reference Manual

ID 683222
Date 11/28/2022
Public

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6.1.4.3. About the SDRAM Scheduler

The SDRAM scheduler functions as an MPFE, scheduling transactions from multiple masters to the SDRAM.

The SDRAM scheduler supports the following masters:

  • The CCU
  • The FPGA-to-SDRAM bridges

The SDRAM scheduler arbitrates among transactions initiated by the masters, and determines the order of operations. The scheduler arbitrates among the masters, ensuring optimal interconnect performance based on configurable quality-of-service settings.

You can configure the SDRAM scheduler through the registers.