Intel® Stratix® 10 Hard Processor System Technical Reference Manual

ID 683222
Date 11/28/2022
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

3.1. Features of the Cortex-A53 MPCore

The ARM® Cortex® -A53 MPCore™ Processor contains four CPUs that implement the ARM® v8-A architecture instruction set. Each CPU has identical integration.

  • Support for 32- and 64-bit instruction sets
  • In-order pipeline with symmetric dual-issue of most instructions
  • ARM® NEON* single instruction, multiple data (SIMD) coprocessor with a floating point unit (FPU)
    • Single- and double-precision IEEE-754 floating point math support
    • Integer and polynomial math support
  • Symmetric multiprocessing (SMP) and asymmetric multiprocessing (AMP) modes
  • ARM® v8 Cryptography Extension
  • Level 1 (L1) cache
    • 32 KB two-way set associative instruction cache
    • Single Error Detect (SED) and parity checking support for L1 instruction cache
    • 32 KB four-way set associative data cache
    • ECC, Single Error Correct, Double Error Detect (SECDED) protection for L1 data cache
  • Memory Management Unit (MMU) that communicates with system MMU (SMMU)
    • 10-entry fully-associative instruction micro translation lookaside buffer (TLB)
    • 10-entry fully-associative data micro TLB
    • 512‑entry unified TLB
  • Generic timer
  • Governor module that controls clock and reset
  • Debug modules
    • Performance Monitor Unit
    • Embedded Trace Macrocell (ETMv4)
    • CoreSight cross trigger interface

Some integration is also shared among the four CPUs in the Cortex® -A53 MPCore processor.

  • 1 MB ARM® L2 cache controller with ECC, SECDED protection
  • Snoop Control Unit (SCU) that maintains coherency between CPUs and communicates with the system CCU
  • Global timer
Modules that the Cortex® -A53 MPCore™ interfaces to in the system include:
  • Generic Interrupt Controller (GIC-400, version r0p1)
  • System cache coherency unit (CCU)
  • System memory management unit (SMMU, ARM MMU-500, version r2p0)
The table below lists the Cortex® -A53 MPCore™ version.
Table 28.   Cortex® -A53 MPCore Module Version

Processor

Version

Cortex-A53 MPCore

r0p4