Intel® Stratix® 10 Hard Processor System Technical Reference Manual
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17.7.2. EMAC FPGA Interface Initialization
In general, the FPGA interface must be active in user mode with valid PHY clocks, the Ethernet Controller must be in a reset state during static configuration and the clock must be active and valid before the Ethernet Controller is brought out of reset.
- After the HPS is released from cold or warm reset, reset the Ethernet Controller module by setting the appropriate emac* bit in the per0modrst register in the Reset Manager.
- Configure the EMAC Controller clock to 250 MHz by programming the appropriate registers in the Clock Manager.
- Bring the Ethernet PHY out of reset to allow PHY to generate RX clocks and TX clocks.
When using FPGA GMII/MII interface, you must have a stable RX clock (emac_clk_rx_i) and TX clock (emac_clk_tx_i) supply from PHY to EMAC before bringing EMAC out of reset.
There are no registers to verify, but you can create the following custom logic block to cross check:- You can use Signal Tap to check, or create a simple counter block with the RX clock and TX clock as clock source to check if it runs.
- If the PTP clock source is from the FPGA, ensure that the FPGA f2h_ptp_ref_clk is active.
- The soft GMII/MII adaptor must be loaded with active clocks propagating. The FPGA must be configured to user mode and a reset to the user soft FPGA IP may be required to propagate the PHY clocks to the HPS.
- Once all clock sources are valid, apply the following clock settings:
- Program the phy_intf_sel field of the emac* register in the System Manager to 0x0 to select GMII/MII PHY interface.
- If the PTP clock source is from the FPGA, set the ptp_clk_sel bit to 0x1 in the emac_global register of the System Manager.
- Enable the Ethernet Controller FPGA interface by setting the emac_* bit in the fpgaintf_en_3 register of the System Manager.
- Configure all of the EMAC static settings if the user requires a different setting from the default value. These settings include the AxPROT[1:0] and AxCACHE signal values which are programmed in the emac* register of the System Manager.
- After confirming the settings are valid, software can clear the emac* bit in the per0modrst register of the Reset Manager to bring the EMAC out of reset..