Intel® Stratix® 10 Hard Processor System Technical Reference Manual

ID 683222
Date 11/28/2022
Public

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14.3.3.4. HPS Oscillator Clock Input Register

Register hps_osc_clk selects the I/O for the external oscillator connection. The HPS routes this input clock from the oscillator to the HPS clock manager. Platform Designer determines the value of the HPS Oscillator Clock Input Register automatically when you configure the HPS component.

At cold reset, hps_osc_clk defaults to value 0x3F, and none of the I/Os are selected. A warm reset event does not affect this register.

Note:

Although the HPS Oscillator Clock Input Register can be configured through the control registers, Intel recommends against reconfiguring this register after I/O configuration is complete.

When a pin is assigned as the oscillator clock input, it cannot support any other peripheral. For this reason, Platform Designer sets the pin MUX register to 8, indicating "not connected to any peripheral".