Intel® Stratix® 10 Hard Processor System Technical Reference Manual

ID 683222
Date 11/28/2022
Public

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7.6.1. FPGA-to-HPS Bridge Clocks and Resets

The master interface of the bridge in the HPS logic operates in the ccu_clk clock domain, which is mpu_clk / 2. The slave interface exposed to the FPGA fabric operates in the fpga2hps_clk clock domain provided by the user logic. The bridge provides clock crossing logic that allows the logic in the FPGA to operate in any clock domain, asynchronous from the HPS.

The FPGA-to-HPS bridge has one reset signal, fpga2hps_bridge_rst_n . The reset manager asserts this signal to the FPGA-to-HPS bridge on a cold or warm reset.