Intel® Stratix® 10 Hard Processor System Technical Reference Manual

ID 683222
Date 11/28/2022
Public

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6.3.3.2. Hard Memory Controller Memory Mapped Registers

The FPGA hard memory controller MMRs are used for determining the state of the hard memory controller interface, and for triggering the hard memory controller into a reset state along with the I/O. The FPGA hard memory controller MMRs can be programmed as secure or non-secure.