Intel® Stratix® 10 Hard Processor System Technical Reference Manual

ID 683222
Date 11/28/2022
Public

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7.4. HPS-to-FPGA Bridge

The HPS-to-FPGA bridge provides a configurable-width, high-performance master interface to the FPGA fabric. The bridge provides most masters in the HPS with access to logic and peripherals implemented in the FPGA. The size of the address space is 4 GB. You can configure the bridge master exposed to the FPGA fabric for 32/64/128-bit data.

The HPS-to-FPGA bridge multiplexes the configured data width from the L3 interconnect to the FPGA interface. The bridge provides width adaptation and clock crossing logic that allows the logic in the FPGA to operate in any clock domain, asynchronous from the HPS.

Table 81.   HPS-to-FPGA Bridge PropertiesThe following table lists the properties of the HPS-to-FPGA bridge, including the configurable master interface exposed to the FPGA fabric.
Bridge Property Value

Data width 10

32, 64, or 128 bits

Clock domain

hps2fpga_clk

Address width

32 bits

ID width

4 bits

Read acceptance

16 transactions

Write acceptance

16 transactions

Total acceptance

16 transactions

The HPS-to-FPGA bridge is configurable in the HPS component parameter editor, available in Platform Designer and the IP Catalog. The HPS component parameter editor allows you to set the data path width and the bridge protocol, according to the FPGA bitstream.

10 The bridge master data width is user-configurable at the time you instantiate the HPS component in your system.