Intel® Stratix® 10 Hard Processor System Technical Reference Manual

ID 683222
Date 11/28/2022
Public

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15.2. NAND Flash Controller Block Diagram and System Integration

Figure 45. NAND Flash Controller System DiagramThis diagram depicts the interfaces of the HPS with the NAND Flash Controller highlighted.

Features of the flash controller:

  • Receives commands and data from the host through memory-mapped control and data registers connected to the command and data slave interface
  • The host accesses the flash controller’s control and status registers (CSRs) through the register slave interface.
  • Handles all command sequencing and flash device interactions
  • Generates interrupts to the HPS Cortex-A53 MPCore™ processor generic interrupt controller (GIC)
  • The DMA master interface provides accesses to and from the flash controller through the controller's built-in DMA.