Intel® Stratix® 10 Hard Processor System Technical Reference Manual

ID 683222
Date 11/28/2022
Public

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6.2.1.1. HPS-to-FPGA Bridge Address Spaces

FPGA Slave Address Space

The FPGA slave address space provides access to soft components implemented in the FPGA core, through the HPS-to-FPGA bridge. The soft logic in the FPGA performs address decoding.

The L3 and MPU regions provide windows of 4 GB into the FPGA slave address space.

The lower 1.5 GB is accessible from 0x00_8000_0000 to 0x00_E000_0000 in the HPS system memory map.

The full 4 GB space is accessible starting at 0x20_0000_0000 in the HPS system memory map. Therefore, the lower 1.5 GB is mapped to two separate addresses in the HPS address space.

Figure 22. FPGA Slave Address Map

Lightweight FPGA Slave Address Map

The lightweight FPGA slave address space provides access to soft components implemented in the FPGA core through the lightweight HPS-to-FPGA bridge. The soft logic in the FPGA performs address decoding.

A portion of the peripheral region provides a window of 2 MB into the FPGA slave address space. The base address of the lightweight FPGA slaves window is mapped to address 0x0 in the FPGA slave address space.