Intel® Stratix® 10 Hard Processor System Technical Reference Manual

ID 683222
Date 11/28/2022
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

16.4.3.1.6. CCS Detection and Interrupt to Host Processor

If the ccs_expected bit in the cmd register is set to 1, the CCS from the CE‑ATA card device is indicated by setting the data transfer over bit (dto) in the rintsts register. The controller generates a DTO interrupt if this interrupt is not masked.

For the RW_MULTIPLE_BLOCK commands, if the CE‑ATA card device interrupts are disabled (the nIEN bit is set to 1 in the ATA control register)— that is, the ccs_expected bit is set to 0 in the cmd register—there are no CCSs from the card. When the data transfer is over—that is, when the requested number of bytes are transferred—the dto bit in the rintsts register is set to 1.