Intel® Stratix® 10 Hard Processor System Technical Reference Manual

ID 683222
Date 11/28/2022
Public

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5.4.2.1. Security State

The ARM® Cortex® -A53 CPUs provide the following security states, each with an associated memory address space:
  • Secure state:
    • The processor can access both the secure memory address space and the non-secure memory address space.
    • When executing at EL3, the processor can access all the system control resources.
  • Non-secure state:
    • The processor can access only the non-secure memory address space.
    • The processor cannot access the secure system control resources.

Depending on the security state, only certain exception levels are allowed.

Table 52.  Exception Level Implementation by Security State
Exception Level Non-secure State Secure State
EL0 Yes Yes
EL1 Yes Yes
EL2 Yes No
EL3 No Yes