Intel® Stratix® 10 Hard Processor System Technical Reference Manual

ID 683222
Date 11/28/2022
Public

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20.4.4.1. Clock Synchronization

When two or more masters try to transfer information on the bus at the same time, they must arbitrate and synchronize the SCL clock. All masters generate their own clock to transfer messages. Data is valid only during the high period of SCL clock. Clock synchronization is performed using the wired-AND connection to the SCL signal. When the master transitions the SCL clock to 0, the master starts counting the low time of the SCL clock and transitions the SCL clock signal to 1 at the beginning of the next clock period. However, if another master is holding the SCL line to 0, then the master goes into a HIGH wait state until the SCL clock line transitions to 1. †

All masters then count off their high time, and the master with the shortest high time transitions the SCL line to 0. The masters then counts out their low time and the one with the longest low time forces the other master into a HIGH wait state. Therefore, a synchronized SCL clock is generated, which is illustrated in the following figure. Optionally, slaves may hold the SCL line low to slow down the timing on the I2C bus. †

Figure 120. Multiple Master Clock Synchronization †
Figure 121. Impact of SCL Rise Time and Fall Time on Generated SCL

The following equations can be used to compute SCL high and low time:

SCL_High_time = [(HCNT + IC_FS_SPKLEN + 6)*ic_clk] + SCL_Fall_time

SCL_Low_time = [(LCNT + 1)*ic_clk] - SCL_Fall_time + SCL_Rise_time