Intel® Stratix® 10 Hard Processor System Technical Reference Manual

ID 683222
Date 11/28/2022
Public

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16.4.2.4. Interrupt Controller Unit

The interrupt controller unit generates an interrupt that depends on the rintsts register, the interrupt mask register (intmask), and the interrupt enable bit (int_enable) of the control register (ctrl). Once an interrupt condition is detected, the controller sets the corresponding interrupt bit in the rintsts register. The bit in the rintsts register remains set until the software clears the bit by writing a 1 to the interrupt bit; writing a 0 leaves the bit untouched.

The interrupt controller unit generates active high, level sensitive interrupts that are asserted only when at least one bit in the rintsts register is set to 1, the corresponding intmask register bit is 1, and the int_enable bit of the ctrl register is 1.

The int_enable bit of the ctrl register is cleared during a power-on reset, and the intmask register bits are set to 0x0000000, which masks all the interrupts.

Table 128.  Interrupt Status Register Bits
Bits Interrupt Description
16 SDIO Interrupts Interrupts from SDIO cards.
15 End Bit Error (read)/Write no CRC (EBE)

Error in end-bit during read operation, or no data CRC received during write operation.

Note: For MMC CMD19, there may be no CRC status returned by the card. Hence, EBE is set for CMD19. The application should not treat this as an error.
14 Auto Command Done (ACD)

Stop/abort commands automatically sent by card unit and not initiated by host; similar to Command Done (CD) interrupt.

Recommendation: Software typically need not enable this for non CE-ATA accesses; Data Transfer Over (DTO) interrupt that comes after this interrupt determines whether data transfer has correctly completed. For CE-ATA accesses, if the software sets send_auto_stop_ccsd bit in the control register, then software should enable this bit.

13 Start Bit Error (SBE)

Error in data start bit when data is read from a card. In 4-bit mode, if all data bits do not have start bit, then this error is set.

12 Hardware Locked write Error (HLE) During hardware-lock period, write attempted to one of locked registers.
11 FIFO Underrun/Overrun Error (FRUN)

Host tried to push data when FIFO was full, or host tried to read data when FIFO was empty. Typically this should not happen, except due to error in software.

Card unit never pushes data into FIFO when FIFO is full, and pop data when FIFO is empty.

If IDMAC (Internal Direct Memory Access Controller) is enabled, FIFO underrun/overrun can occur due to a programming error on MSIZE and watermark values in FIFOTH register; for more information, refer to Internal Direct Memory Access Controller (IDMAC) section in the "Synopsys DesignWare Cores Mobile Storage Host Databook".

10 Data Starvation by Host Timeout (HTO)

To avoid data loss, card clock out (cclk_out) is stopped if FIFO is empty when writing to card, or FIFO is full when reading from card. Whenever card clock is stopped to avoid data loss, data-starvation timeout counter is started with data-timeout value. This interrupt is set if host does not fill data into FIFO during write to card, or does not read from FIFO during read from card before timeout period.

Even after timeout, card clock stays in stopped state, with CIU state machines waiting. It is responsibility of host to push or pop data into FIFO upon interrupt, which automatically restarts cclk_out and card state machines.

Even if host wants to send stop/abort command, it still must ensure to push or pop FIFO so that clock starts in order for stop/abort command to send on cmd signal along with data that is sent or received on data line.

9 Data Read Timeout (DRTO)/Boot Data Start (BDS)
  • In Normal functioning mode: Data read timeout (DRTO) Data timeout occurred. Data Transfer Over (DTO) also set if data timeout occurs.
  • In Boot Mode: Boot Data Start (BDS) When set, indicates that SD/MMC controller has started to receive boot data from the card. A write to this register with a value of 1 clears this interrupt.
8 Response Timeout (RTO)/ Boot Ack Received (BAR)
  • In Normal functioning mode: Response timeout (RTO) Response timeout occurred. Command Done (CD) also set if response timeout occurs. If command involves data transfer and when response times out, no data transfer is attempted by SD/MMC controller.
  • In Boot Mode: Boot Ack Received (BAR) When expect_boot_ack is set, on reception of a boot acknowledge pattern—0-1-0—this interrupt is asserted. A write to this register with a value of 1 clears this interrupt.
7 Data CRC Error (DCRC)

Received Data CRC does not match with locally-generated CRC in CIU; expected when a negative CRC is received.

6 Response CRC Error (RCRC)

Response CRC does not match with locally-generated CRC in CIU.

5 Receive FIFO Data Request (RXDR)

Interrupt set during read operation from card when FIFO level is greater than Receive-Threshold level.

Recommendation: In DMA modes, this interrupt should not be enabled.

ISR, in non-DMA mode:
pop RX_WMark + 1 data from FIFO
4 Transmit FIFO Data Request (TXDR)

Interrupt set during write operation to card when FIFO level reaches less than or equal to Transmit-Threshold level.

Recommendation: In DMA modes, this interrupt should not be enabled.

ISR in non-DMA mode:


   if (pending_bytes > \
   (FIFO_DEPTH - TX_WMark))
        push (FIFO_DEPTH - \
        TX_WMark) data into FIFO
   else
        push pending_bytes data \
        into FIFO
3 Data Transfer (DTO)

Data transfer completed, even if there is Start Bit Error or CRC error. This bit is also set when “read data-timeout” occurs or CCS is sampled from CE-ATA device.

Recommendation: In non-DMA mode, when data is read from card, on seeing interrupt, host should read any pending data from FIFO. In DMA mode, DMA controllers guarantee FIFO is flushed before interrupt.

Note: DTO bit is set at the end of the last data block, even if the device asserts MMC busy after the last data block.
2 Command Done (CD)

Command sent to card and received response from card, even if Response Error or CRC error occurs. Also set when response timeout occurs or CCSD sent to CE-ATA device.

1 Response Error (RE)

Error in received response set if one of following occurs:

  • Transmission bit != 0
  • Command index mismatch
  • End-bit != 1
0 Card-Detect (CDT)

When one or more cards inserted or removed, this interrupt occurs. Software should read card-detect register (CDETECT, 0x50) to determine current card status.

Recommendation: After power-on and before enabling interrupts, software should read card detect register and store it in memory. When interrupt occurs, it should read card detect register and compare it with value stored in memory to determine which card(s) were removed/inserted. Before exiting ISR, software should update memory with new card-detect value.