Stratix® 10 Hard Processor System Technical Reference Manual

ID 683222
Date 8/15/2024
Public
Document Table of Contents

2.2.6.1.1. Stratix 10 HPS SDRAM Scheduler

The SDRAM scheduler accepts read and write requests from the processor, HPS peripheral masters, and soft logic in the FPGA (through the FPGA-to-SDRAM interface). It is programmed with memory timings, allowing it to optimize memory accesses.