Intel® Stratix® 10 Hard Processor System Technical Reference Manual

ID 683222
Date 1/25/2024
Public
Document Table of Contents

12.2. Modules Under Reset

This table depicts which modules undergo reset during different reset scenarios.
Table 106.  Modules Under Reset
Modules/ Resources POR System Cold Reset System Warm Reset Watchdog Reset MPU Cold Reset CPU Cold Reset CPU Warm Reset JTAG TAP Reset Debug Reset
HPS registers X - - - - - - - -
HPS-to-FPGA reset signals X X X X - - - - -
System Interconnect, CCU X X - X - - - - -
Reset Manager, Clock Manager, System Manager X X 26 X26 X26 - - - - -
Peripherals X X X X - - - - -
L2/SCU X X X X X - - - -
Bridges X X - X - - - - -
MPU cores X X X X X X 27 X27 - -
MPU Debug X X - - X X27 - - X
Non-MPU Debug/Trace X X - - - - - - X
JTAG TAP X - - - - - - X -
26 Only clock and reset manager registers are reset. For more information about the specific register, refer to Clock/Reset Manager Address Map and Register Definitions.
27 Only the CPUs that are selected through the COLDMODRST/MPUMODRST register is reset.