Intel® Stratix® 10 Hard Processor System Technical Reference Manual

ID 683222
Date 1/25/2024
Public
Document Table of Contents

9.3.5.1. Pipeline and Timing

The RAM controller is a pipelined design, where:
  • The Write path (full width) pipeline is two stages deep; therefore providing a two clock latency.
  • The Write path (subword access) pipeline is three stages deep to account for the read-modify-write.
  • The Read path pipeline is four stages deep for RAM.