Stratix® 10 Hard Processor System Technical Reference Manual

ID 683222
Date 8/15/2024
Public
Document Table of Contents

3.5.13. Generic Interrupt Controller

The Arm* Generic Interrupt Controller (GIC-400) resides within the system complex outside of the Cortex* -A53 processor. The GIC is shared by all of the Cortex* -A53 CPUs.

The GIC has software-configurable settings to detect, manage and distribute interrupts in the SoC.

  • Interrupts are enabled or disabled and prioritized through control registers.
  • Interrupts can be prioritized and signaled to different processors.
  • You can configure interrupts as secure or non-secure by assigning them to group 0 or group1, respectively.
  • Virtualization extensions within the GIC allow you to manage virtualized interrupts.
The GIC provides 205 shared interrupt sources, including dedicated peripherals and IP implemented in the FPGA fabric. Each CPU also has six external private peripheral interrupts and one internal private peripheral interrupt. All four CPUs share 16 banked software-generated interrupts (SGIs).
Note: Legacy IRQs are not supported by the GIC.