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1. Stratix® 10 Hard Processor System Technical Reference Manual Revision History
2. Introduction to the Hard Processor System
3. Cortex-A53 MPCore Processor
4. Cache Coherency Unit
5. System Memory Management Unit
6. System Interconnect
7. HPS-FPGA Bridges
8. DMA Controller
9. On-Chip RAM
10. Error Checking and Correction Controller
11. Clock Manager
12. Reset Manager
13. System Manager
14. Hard Processor System I/O Pin Multiplexing
15. NAND Flash Controller
16. SD/MMC Controller
17. Ethernet Media Access Controller
18. USB 2.0 OTG Controller
19. SPI Controller
20. I2C Controller
21. UART Controller
22. General-Purpose I/O Interface
23. Timers
24. Watchdog Timers
25. CoreSight Debug and Trace
A. Booting and Configuration
B. Accessing the Secure Device Manager Quad SPI Flash Controller through HPS
C. Operational Status of the HPS to the FPGA Logic
2.2.1. HPS Block Diagram
2.2.2. Cortex-A53 MPCore Processor
2.2.3. Cache Coherency Unit
2.2.4. System Memory Management Unit
2.2.5. HPS Interfaces
2.2.6. System Interconnect
2.2.7. On-Chip RAM
2.2.8. Flash Memory Controllers
2.2.9. System Modules
2.2.10. Interface Peripherals
2.2.11. CoreSight* Debug and Trace
2.2.12. Hard Processor System I/O Pin Multiplexing
3.5.1. Exception Levels
3.5.2. Virtualization
3.5.3. Memory Management Unit
3.5.4. Level 1 Caches
3.5.5. Level 2 Memory System
3.5.6. Snoop Control Unit
3.5.7. Cryptographic Extensions
3.5.8. NEON Multimedia Processing Engine
3.5.9. Floating Point Unit
3.5.10. ACE Bus Interface
3.5.11. Abort Handling
3.5.12. Cache Protection
3.5.13. Generic Interrupt Controller
3.5.14. Generic Timers
3.5.15. Debug Modules
3.5.16. Cache Coherency Unit
3.5.17. Clock Sources
5.4.1. Translation Stages
5.4.2. Exception Levels
5.4.3. Translation Regimes
5.4.4. Translation Buffer Unit
5.4.5. Translation Control Unit
5.4.6. Security State Determination
5.4.7. Stream ID
5.4.8. Quality of Service Arbitration
5.4.9. System Memory Management Unit Interrupts
5.4.10. System Memory Management Unit Reset
5.4.11. System Memory Management Unit Clocks
6.2.1. Stratix 10 System Interconnect Address Spaces
6.2.2. Secure Transaction Protection
6.2.3. Stratix 10 HPS System Interconnect Master Properties
6.2.4. Stratix 10 HPS System Interconnect Slave Properties
6.2.5. System Interconnect Clocks
6.2.6. Stratix 10 HPS System Interconnect Resets
6.2.7. Functional Description of the Rate Adapters
6.2.8. Functional Description of the Firewalls
6.2.9. Functional Description of the SDRAM L3 Interconnect
6.2.10. Functional Description of the Arbitration Logic
6.2.11. Functional Description of the Observation Network
7.1. Features of the HPS-FPGA Bridges
7.2. HPS-FPGA Bridges Block Diagram and System Integration
7.3. FPGA-to-HPS Bridge
7.4. HPS-to-FPGA Bridge
7.5. Lightweight HPS-to-FPGA Bridge
7.6. Clocks and Resets
7.7. Data Width Sizing
7.8. Ready Latency Support
7.9. HPS-FPGA Bridges Address Map and Register Definitions
15.1. NAND Flash Controller Features
15.2. NAND Flash Controller Block Diagram and System Integration
15.3. NAND Flash Controller Signal Descriptions
15.4. Functional Description of the NAND Flash Controller
15.5. NAND Flash Controller Programming Model
15.6. NAND Flash Controller Address Map and Register Definitions
15.5.1.1. NAND Flash Controller Optimization Sequence
15.5.1.2. Device Initialization Sequence
15.5.1.3. Device Operation Control
15.5.1.4. ECC Enabling
15.5.1.5. NAND Flash Controller Performance Registers
15.5.1.6. Interrupt and DMA Enabling
15.5.1.7. Timing Registers
15.5.1.8. Registers to Ignore
16.1. Features of the SD/MMC Controller
16.2. SD/MMC Controller Block Diagram and System Integration
16.3. SD/MMC Controller Signal Description
16.4. Functional Description of the SD/MMC Controller
16.5. SD/MMC Controller Programming Model
16.6. SD/MMC Controller Address Map and Register Definitions
16.4.2.5.1. Internal DMA Controller Descriptors
16.4.2.5.2. Internal DMA Controller Descriptor Address
16.4.2.5.3. Internal DMA Controller Descriptor Fields
16.4.2.5.4. Host Bus Burst Access
16.4.2.5.5. Host Data Buffer Alignment
16.4.2.5.6. Buffer Size Calculations
16.4.2.5.7. Internal DMA Controller Interrupts
16.4.2.5.8. Internal DMA Controller Functional State Machine†
16.4.3.1.1. Load Command Parameters
16.4.3.1.2. Send Command and Receive Response
16.4.3.1.3. Send Response to BIU
16.4.3.1.4. Driving P-bit to the CMD Pin
16.4.3.1.5. Polling the CCS
16.4.3.1.6. CCS Detection and Interrupt to Host Processor
16.4.3.1.7. CCS Timeout
16.4.3.1.8. Send CCSD Command
16.4.3.1.9. I/O transmission delay (NACIO Timeout)
16.5.1. Software and Hardware Restrictions†
16.5.2. Initialization
16.5.3. Controller/DMA/FIFO Buffer Reset Usage
16.5.4. Non-Data Transfer Commands
16.5.5. Data Transfer Commands
16.5.6. Transfer Stop and Abort Commands
16.5.7. Internal DMA Controller Operations
16.5.8. Commands for SDIO Card Devices
16.5.9. CE-ATA Data Transfer Commands
16.5.10. Card Read Threshold
16.5.11. Interrupt and Error Handling
16.5.12. Booting Operation for eMMC and MMC
16.5.12.1. Boot Operation by Holding Down the CMD Line
16.5.12.2. Boot Operation for eMMC Card Device
16.5.12.3. Boot Operation for Removable MMC4.3, MMC4.4 and MMC4.41 Cards
16.5.12.4. Alternative Boot Operation
16.5.12.5. Alternative Boot Operation for eMMC Card Devices
16.5.12.6. Alternative Boot Operation for MMC4.3 Cards
17.1. Features of the Ethernet MAC
17.2. EMAC Block Diagram and System Integration
17.3. Distributed Virtual Memory Support
17.4. EMAC Controller Signal Description
17.5. EMAC Internal Interfaces
17.6. Functional Description of the EMAC
17.7. Ethernet MAC Programming Model
17.8. Ethernet MAC Address Map and Register Definitions
17.6.1. Transmit and Receive Data FIFO Buffers
17.6.2. DMA Controller
17.6.3. Descriptor Overview
17.6.4. IEEE 1588-2002 Timestamps
17.6.5. IEEE 1588-2008 Advanced Timestamps
17.6.6. IEEE 802.3az Energy Efficient Ethernet
17.6.7. Checksum Offload
17.6.8. Frame Filtering
17.6.9. Clocks and Resets
17.6.10. Interrupts
17.6.8.1.1. Unicast Destination Address Filter
17.6.8.1.2. Multicast Destination Address Filter
17.6.8.1.3. Hash or Perfect Address Filter
17.6.8.1.4. Broadcast Address Filter
17.6.8.1.5. Unicast Source Address Filter
17.6.8.1.6. Inverse Filtering Operation (Invert the Filter Match Result at Final Output)
17.6.8.1.7. Destination and Source Address Filtering Summary
17.7.1. System Level EMAC Configuration Registers
17.7.2. EMAC FPGA Interface Initialization
17.7.3. EMAC HPS Interface Initialization
17.7.4. DMA Initialization
17.7.5. EMAC Initialization and Configuration
17.7.6. Performing Normal Receive and Transmit Operation
17.7.7. Stopping and Starting Transmission
17.7.8. Programming Guidelines for Energy Efficient Ethernet
17.7.9. Programming Guidelines for Flexible Pulse-Per-Second (PPS) Output
18.1. Features of the USB OTG Controller
18.2. Block Diagram and System Integration
18.3. Distributed Virtual Memory Support
18.4. USB 2.0 ULPI PHY Signal Description
18.5. Functional Description of the USB OTG Controller
18.6. USB OTG Controller Programming Model
18.7. USB 2.0 OTG Controller Address Map and Register Definitions
24.4.1. Setting the Timeout Period Values
24.4.2. Selecting the Output Response Mode
24.4.3. Enabling and Initially Starting a Watchdog Timers
24.4.4. Reloading a Watchdog Counter
24.4.5. Pausing a Watchdog Timers
24.4.6. Disabling and Stopping a Watchdog Timers
24.4.7. Watchdog Timers State Machine
25.1. Features of CoreSight Debug and Trace
25.2. Arm* CoreSight Documentation
25.3. CoreSight Debug and Trace Block Diagram and System Integration
25.4. Functional Description of CoreSight Debug and Trace
25.5. CoreSight Debug and Trace Programming Model
25.6. CoreSight Debug and Trace Address Map and Register Definitions
25.4.1. Debug Access Port
25.4.2. CoreSight SoC-400 Timestamp Generator
25.4.3. System Trace Macrocell
25.4.4. Trace Funnel
25.4.5. CoreSight Trace Memory Controller
25.4.6. AMBA Trace Bus Replicator
25.4.7. Trace Port Interface Unit
25.4.8. NoC Trace Ports
25.4.9. Embedded Cross Trigger System
25.4.10. Embedded Trace Macrocell
25.4.11. HPS Debug APB Interface
25.4.12. FPGA Interface
25.4.13. Debug Clocks
25.4.14. Debug Resets
B.1. Features of the Quad SPI Flash Controller
B.2. Taking Ownership of Quad SPI Controller
B.3. Quad SPI Flash Controller Block Diagram and System Integration
B.4. Quad SPI Flash Controller Signal Description
B.5. Functional Description of the Quad SPI Flash Controller
B.6. Quad SPI Flash Controller Programming Model
B.7. Accessing the SDM Quad SPI Flash Controller Through HPS Address Map and Register Definitions
B.5.1. Overview
B.5.2. Data Slave Interface
B.5.3. SPI Legacy Mode
B.5.4. Register Slave Interface
B.5.5. Local Memory Buffer
B.5.6. Arbitration between Direct/Indirect Access Controller and STIG
B.5.7. Configuring the Flash Device
B.5.8. XIP Mode
B.5.9. Write Protection
B.5.10. Data Slave Sequential Access Detection
B.5.11. Clocks
B.5.12. Resets
B.5.13. Interrupts
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17.6.8.3. Layer 3 and Layer 4 Filters
Layer 3 filtering refers to source address and destination address filtering. Layer 4 filtering refers to source port and destination port filtering. The frames are filtered in the following ways:†
- Matched frames†
- Unmatched frames†
- Non-TCP or UDP IP frames†