Visible to Intel only — GUID: zbr1481129873337
Ixiasoft
Visible to Intel only — GUID: zbr1481129873337
Ixiasoft
14.3.3.1. Stratix® 10 Dedicated Pin MUX Registers
The HPS provides pin MUX registers, pin0sel through pin47sel, for each of the dedicated pins HPS_IOA_0 to HPS_IOA_23 and HPS_IOB_0 to HPS_IOB_23. Each pin MUX register contains a 4-bit MUX select field to select the function of the dedicated pin. A cold reset event sets these fields to 9 (reserved). Before a pin can connect to an HPS peripheral, the bootloader must reconfigure the MUX select field.
A warm reset event does not affect the dedicated pin MUX registers.
Platform Designer determines the values of the pin MUX registers automatically when you configure the HPS component.