Stratix® 10 Hard Processor System Technical Reference Manual
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4.5.3. I/O Coherency Bridge
These masters send both non-coherent and I/O coherent traffic to the IOCB. If a master issues a WriteUnique or WriteLineUnique ACE protocol request and that address corresponds to a cache line, the IOCB notifies the Cortex* -A53 MPCore processor to invalidate that data. The IOCB prefetches coherent permissions for requests from the coherency directory so that it can execute these requests in parallel with non-coherent requests and maintain high bandwidth.