Intel® Stratix® 10 Hard Processor System Technical Reference Manual

ID 683222
Date 1/25/2024
Public
Document Table of Contents

6.2. Functional Description of the Stratix 10 HPS System Interconnect

The system interconnect, in conjunction with the system MMU (SMMU), provides access to a 132-GB address space.

Note: If your design uses a peripheral master without the SMMU, the master can only access the first 4 GB of the address space.

Address spaces are divided into one or more regions.

The following figure shows the relationships between the HPS address spaces. The figure is not to scale.

Figure 21. HPS Address Space Relationships

The table below shows the HPS address spaces and the masters that access those address spaces.

Table 58.  Stratix 10 HPS Address Space Map Master Views and FPGA Slave Regions
Name Size Type (Physical/Virtual) Masters
MPU view of the HPS/MPU address map 132 GB P/V MPU and FPGA-to-HPS bridge
L3 NoC view of the HPS/MPU address map 4 GB 6 P All L3 masters
132 GB V All L3 masters, with SMMU enabled
FPGA Slaves region of the HPS/MPU address map 4 GB P All masters accessing the HPS-to-FPGA bridge
Lightweight FPGA Slave region of the HPS/MPU address map 2 MB P All masters accessing the lightweight HPS-to-FPGA bridge
FPGA to SDRAM Interface view of the DDR address map 128 GB P FPGA masters accessing HPS SDRAM through the FPGA-to-SDRAM interfaces
6 The bottom 4 GB of the full 132 GB region