Stratix® 10 Hard Processor System Technical Reference Manual

ID 683222
Date 8/15/2024
Public
Document Table of Contents

2.1. Features of the HPS

The main modules of the HPS are:

  • Quad-core Arm* Cortex*-A53 MPCore processor
  • Cache Coherency Unit (CCU)
  • System Memory Management Unit (SMMU)
  • System interconnect that includes:
    • Three memory-mapped interfaces between the HPS and FPGA:
      • HPS-to-FPGA bridge: 32-, 64-, or 128-bit wide Arm* Advanced Microcontroller Bus Architecture ( AMBA* ) Advanced eXtensible Interface ( AXI* )-4
      • Lightweight HPS-to-FPGA bridge: 32-bit wide AXI* -4
      • FPGA-to-HPS bridge: 128-bit wide AXI Coherency Extensions-Lite (ACE-Lite)
    • Three memory-mapped FPGA-to-SDRAM AXI* -4 interfaces, 32, 64, or 128 bits wide, allow the FPGA to directly share the HPS-connected SDRAM
  • General-purpose direct memory access (DMA) controller
  • 256 KB on-chip RAM
  • Error checking and correction controllers for on-chip RAM and peripheral RAMs
  • Clock manager
  • Reset manager
  • System manager
  • Dedicated I/O pin multiplexer (MUX)
  • NAND flash controller
  • Secure digital/multimedia card (SD/MMC) controller
  • Three Ethernet media access controllers (EMACs)
  • Two USB 2.0 on-the-go (OTG) controllers
  • Two serial peripheral interface (SPI) master controllers
  • Two SPI slave controllers
  • Five inter-integrated circuit (I2C) controllers:
    • Three can provide support for EMAC
    • Two for general purpose
  • Two UARTs
  • Two general-purpose I/O (GPIO) interfaces with a total of 48 dedicated I/O
  • Four system timers
  • Four watchdog timers
  • Arm* CoreSight* debug components:
    • Debug access port (DAP)
    • Trace port interface unit (TPIU)
    • System trace macrocell (STM)
    • Embedded trace macrocell (ETM)
    • Embedded trace router (ETR)
    • Embedded cross trigger (ECT)