Stratix® 10 Hard Processor System Technical Reference Manual

ID 683222
Date 8/15/2024
Public
Document Table of Contents

6.2.5.1.1. Main Clock Domain

The main domain is largest synchronous domain in the interconnect, containing most of the datapath. The main domain generally consists of a single free-running clock and divided clocks with enables. Resets in the main domain depend on clock groups. Each clock group in the table below uses a single reset. Paths crossing different groups also cross asynchronous reset domains.

Table 66.  Clocks in the Main Clock Domain
Group Clock Clock Divider Reset Usage
main l3_main_free_clk - l3_rst_n clocks most of the interconnect datapath
l4_main_clk 1 DMAC and SPI
l4_mp_clk 2 EMAC, SDMMC, NAND, USB, ECC
l4_sp_clk 4 L4_SP bus
l4_sys_clk 4 L4_SYS bus
syscfg l4_sys_clk 4 syscfg_rst_n L4_SHR and L4_SEC buses
dbg cs_at_clk 1 dbg_rst_n  CoreSight
cs_pdbg_clk 2 CoreSight