Intel® Stratix® 10 Hard Processor System Technical Reference Manual

ID 683222
Date 1/25/2024
Public
Document Table of Contents

3.6.2. Bringing the Cortex* -A53 MPCore out of Reset

When a cold or warm reset is issued to the Arm* Cortex* -A53 MPCore Processor, all cores: CPU0, CPU1, CPU2, and CPU3 reset signals are released from reset automatically.

A cold reset, resets the entire Arm* Cortex* -A53 MPCore, including any debug functionality. A warm reset, resets all of the MPCore, except for the debug logic.

Table 40.  Reset Combinations
Reset Type Description
HPS cold reset The Arm* Cortex* -A53 MPCore Processor is held in reset and powered down.
HPS cold reset with active debug Each of the four cores in the Arm* Cortex* -A53 MPCore Processor are held in reset. The L2 cache is held in reset but powered. Debug is enabled.
Individual Arm* v8-A core cold reset with active debug One of the four cores is in held in reset so that it can be powered. The L2 cache and debug are released from reset. This configuration enables external debug over power down for the core that is held in reset.
Individual Arm* v8-A core warm reset with trace enabled and active debug One of the four cores is held in reset and debug is active.