Stratix® 10 Hard Processor System Technical Reference Manual

ID 683222
Date 8/15/2024
Public
Document Table of Contents

11.3.2. PLL Integration

The two PLLs contain exactly the same set of output clocks. PLL0 is intended to be used for the MPU and NOC clocks. PLL1 outputs are routed to the HPS master peripherals.

Figure 40. PLL Integration in Clock Manager
Table 98.  PLL Direct OutputsFor Boot mode, the maximum and minimum frequency is 200 MHz and 10 MHz respectively.
PLL Output Counter Clock Name Description
Main PLL C0 main_mpu_base_clk Main MPU Base: VCO/2
C1 main_noc_base_clk Main NOC Interconnect base
C2 main_emaca_clk Main EMAC A base
C3 main_emacb_clk Main EMAC B base
C4 main_emac_ptp_clk Main PTP Timestamp base
C5 main_gpio_db_clk Main FPGA Reference base
C6 main_sdmmc_clk Main SDMMC Reference base
C7 main_h2f_user0_clk Main FPGA reference User0 base
C8 main_h2f_user1_clk Main FPGA reference User1 base
C9 Reserved Reserved
Peripheral PLL C0 peri_mpu_base_clk Peripheral MPU Base; VCO/2
C1 peri_noc_base_clk Peripheral NOC Interconnect base
C2 peri_emaca_clk Peripheral EMAC A (250 MHz) base
C3 peri_emacb_clk Peripheral EMAC B (50 MHz) base
C4 peri_emac_ptp_clk Peripheral PTP Timestamp base
C5 peri_gpio_db_clk Peripheral FPGA Reference base
C6 peri_sdmmc_clk Peripheral SDMMC Reference base
C7 peri_h2f_user0_clk Peripheral FPGA reference User0 base
C8 peri_h2f_user1_clk Peripheral FPGA reference User1 base
C9 Reserved Reserved