Stratix® 10 Hard Processor System Technical Reference Manual

ID 683222
Date 8/15/2024
Public
Document Table of Contents

17.1.5. PHY Interface

Different external PHY interfaces are provided depending on whether the Ethernet Controller signals are routed through the HPS I/O pins or the FPGA I/O pins.

The PHY interfaces supported using the HPS I/O pins are:

  • Reduced Media Independent Interface (RMII)
  • Reduced Gigabit Media Independent Interface (RGMII)
The PHY interfaces supported using the FPGA I/O pins are:
  • Media Independent Interface (MII)
  • Gigabit Media Independent Interface (GMII)
  • Reduced Media Independent Interface (RMII) with additional required adaptor logic
    Note: Additional adaptor logic for RMII not provided.
  • Serial Gigabit Media Independent Interface (SGMII) supported through transceiver I/O or high-speed low-voltage differential signaling (LVDS) with soft clock data recover (CDR) I/O with additional required adaptor logic
The Ethernet Controller has two choices for the management control interface used for configuration and status monitoring of the PHY:
  • Management Data Input/Output (MDIO)
  • I2C PHY management through a separate I2C module within the HPS