Intel® Stratix® 10 Hard Processor System Technical Reference Manual

ID 683222
Date 1/25/2024
Public
Document Table of Contents

6.2.8.1.3. Stratix 10 HPS Master Security

All masters on the system interconnect are expected to drive the Secure bit attribute for every transaction.

Table 73.  Master Security Bit
Master Secure bit Secure State Non Secure State Source
AXI-AP A*PROT[1] 0 1 Driven by AXI-AP
CCU_IOS A*PROT[1] 0 1 Driven by CCU (transported from MPU and FPGA2SOC)
DMAC A*PROT[1] 0 1 Driven by DMAC
EMACx A*PROT[1] 0 1 Driven by Sys Mgr
EMAC_TBU A*PROT[1] 0 1 Driven by TBU (transported from EMAC or page table attribute)
ETR A*PROT[1] 0 1 Driven by ETR
ETR_TBU A*PROT[1] 0 1 Driven by TBU (transported from ETR or page table attribute)
NAND A*PROT[1] 0 1 Driven by Sys Mgr
SD/MMC HA*USER[1] 0 1 Driven by Sys Mgr
USB HA*USER[1] 0 1 Driven by Sys Mgr
IO_TBU A*PROT[1] 0 1 Driven by TBU (transported or page table attribute)
SDM_TBU A*PROT[1] 0 1

Driven by TBU (transported from page table attribute)

Accesses to secure slaves by non-secure masters result in a bus error.