Stratix® 10 Hard Processor System Technical Reference Manual

ID 683222
Date 8/15/2024
Public
Document Table of Contents

15.4.5. Clocks

The software enable for NAND is nand_clk_en and is set to ENABLE by default. Also, during the automatic initialization performed after getting out of reset, nand_clk_en is active to ensure that all clocks are active if RAM is cleared for security.

Figure 46. NAND Clocking Diagram
Note: When routing the NAND interface to the FPGA it may be necessary to increase the value of max_rd_delay to compensate for the additional delay between the controller and the FPGA I/O.