Stratix® 10 Hard Processor System Technical Reference Manual

ID 683222
Date 8/15/2024
Public
Document Table of Contents

4.5.1. Bridges

Bridges reside between agent ports and routers in the coherency interconnect of the CCU.

The bridges provide conversions between the port's signal protocol and the coherency interconnect's packet format. Each bridge also performs width conversion and FIFO status tracking.

Each bridge has a set of corresponding registers that you can configure. All of the registers for a bridge configuration begin with a specific bridge register prefix.

Table 42.  CCU Bridges
Bridge Bridge Register Prefix Bridge Description
Cortex* -A53 MPCore bridge bridge_cpu0_mprt_0_37 Bridges the Cortex* -A53 MPCore processor to the coherency interconnect
FPGA-to-HPS bridge bridge_fpga1acel_mprt_4_118 Bridges the FPGA-to-HPS interface to the coherency interconnect
TCU bridge bridge_tcu_mprt_3_70 Bridges the TCU to the coherency interconnect
Peripheral master bridge bridge_iom_mprt_5_63 Bridges the master peripherals in the L3 interconnect to the coherency interconnect.
SDRAM registers bridge bridge_ddrreg_sprt_8_118 Bridges the coherency interconnect to the SDRAM register interface
GIC bridge bridge_gic_sprt_10_100 Bridges the coherency interconnect to the generic interrupt controller (GIC)
Peripheral slave bridge bridge_ios_sprt_12_63 Bridges the coherency interconnect to the peripheral slaves in the L3 interconnect.
SDRAM bridge bridge_mem0_sprt_13_118 Bridges the coherency interconnect to the external SDRAM
On-chip RAM bridge bridge_ram_sprt_14_80 Bridges the coherency interconnect to the on-chip RAM