Stratix® 10 Hard Processor System Technical Reference Manual

ID 683222
Date 8/15/2024
Public
Document Table of Contents

11.1. Features of the Clock Manager

The Clock Manager offers the following features:

  • Generates and manages clocks in the HPS
  • Contains the following clock groups:
    • MPU clock group:
      • Cortex A-53 MPCore, CCU, GIC, and SMMU components
    • NOC clock group:
      • L3 clocks
      • CoreSight clocks
      • L4 clocks
    • Peripheral clock group:
      • GPIO clocks
      • EMAC0/1/2 clocks
      • SDMMC clocks
      • HPS-to-FPGA clocks
    • Other peripherals (NAND, SPI, USB) connect to NOC clocks (L3/L4).
  • Contains two identical 9-output flexible PLL blocks to drive any of the above clocks:
    • Main PLL
    • Peripheral PLL
  • Generates clock gate controls for enabling and disabling most clocks
  • Initializes and sequences clocks
  • Allows software to program clock characteristics, such as the following items discussed later in this chapter:
    • Input clock source for the two PLLs
    • Multiplier range, divider range, and 10 post-scale counters for each PLL
    • VCO calibration for each PLL
    • Bypass modes for each PLL
    • Gate of individual clocks in all PLL clock groups and clock slices.
    • Boot mode for hardware-managed clocks
    • General-purpose I/O (GPIO) debounce clock divide
  • Supports interrupting the Cortex-A53 MPCore on PLL-lock and loss-of-lock.
You must use Platform Designer to configure HPS clock functionality, sources, outputs and frequency values. Platform Designer checks your HPS clock configuration and generate handoff information for boot firmware generation tools to ensure the following requirements are met:
  • Routing of FPGA-to-HPS and HPS-to-FPGA clocks. Platform Designer is responsible for routing and configuring clocks between the HPS. Only the HPS-to-FPGA clock are managed within the clock manager.
  • Software must not program the clock manager with illegal values. If it does, the behavior of the clock manager is undefined and could stop the operation of the HPS. The only guaranteed means for recovery from an illegal clock setting is a cold reset.
  • When re-programming clock settings, there are no automatic glitch-free clock transitions. Software must follow a specific sequence to ensure glitch-free clock transitions. Refer to Hardware-Managed and Software-Managed Clocks section of this chapter.