Stratix® 10 Hard Processor System Technical Reference Manual

ID 683222
Date 8/15/2024
Public

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Document Table of Contents

23.3.1. Clocks

Table 214.  Timers Clock Characteristics

Timers

System Clock

Notes

System timer 0

sys_timer0 l4_sys_free_clk

_

System timer 1

sys_timer1

SP timer 0

sp_timer0 l4_sp_clk

Timers must be disabled if clock frequency changes

SP timer 1

sp_timer1

The timers above are labeled according to the clock they receive. The system timers are connected to the L4_SYS bus and clocked by the l4_sys_free_clk. The SP timers are connected to the L4_SP bus and clocked by l4_sp_clk.

SP timer 0 and SP timer 1 must be disabled before l4_sp_clk is changed to another frequency. You can then re-enable the timer once the clock frequency change takes effect.