Stratix® 10 Hard Processor System Technical Reference Manual

ID 683222
Date 8/15/2024
Public
Document Table of Contents

6.2.3.2. Stratix 10 HPS Cacheable Transfer Routing

When an L3 system interconnect master initiates a transaction, the interconnect determines whether the access is cacheable or non-cacheable. If the transaction is a cacheable access, the interconnect routes it to the CCU.

Masters on the L3 system interconnect can initiate coherent transactions in the interconnect slave address range. For example, as a system designer you can connect an SDRAM interface in the HPS-to-FPGA address range, and ensure coherent access for all masters.

To initiate a coherent transaction, set A*DOMAIN to 2'b01 (inner shareable) or 2'b10 (outer shareable). When it sees any transaction marked shareable, the interconnect logic routes it to the CCU, regardless of the transaction address.