Intel® Stratix® 10 Hard Processor System Technical Reference Manual

ID 683222
Date 1/25/2024
Public
Document Table of Contents

6.1. About the System Interconnect

The system interconnect has the following characteristics:

  • Arm* TrustZone* -compliant security firewalls
    • For each peripheral, implements secure or non-secure access
    • Optionally configures individual transactions as secure or non-secure at the initiating master
    • For certain peripherals, optionally implements two levels of access: privileged or user
  • Three tiers of connectivity:
    • The main level 3 (L3) interconnect—Provides high-bandwidth routing between masters and slaves in the HPS.
    • The SDRAM L3 interconnect—Provides access to a hard memory controller in the FPGA fabric. A multiport front end (MPFE) scheduler enables multiple masters, in both the HPS and FPGA portions of the SoC device, to share the external SDRAM.
    • The level 4 (L4) buses—Independent buses handling:
      • Data traffic for low- to mid-level bandwidth slave peripherals
      • Accesses to peripheral control and status registers throughout the address map
      • Multiple masters from HPS and FPGA to share the SDRAM
      The L4 buses are divided among several clock domains.
  • Quality of service (QoS) with three programmable levels of service on a per-master basis.
  • Byte oriented address handling.
  • Data bus width up to 128 bits.