Stratix® 10 Hard Processor System Technical Reference Manual

ID 683222
Date 8/15/2024
Public
Document Table of Contents

B.5.11. Clocks

The quad SPI controller uses an input clock called qspi_ref_clk. The qspi_clk output clock to the flash device is derived by dividing down the qspi_ref_clk clock by the baud rate divisor field (bauddiv) of the cfg register.

The value of the qspi_ref_clk is determined by the SDM based on the desired Active Serial (AS) configuration clock value you selected in Quartus® Prime.

You can set this value by following these steps:
  1. Open project in Quartus® Prime Pro Edition.
  2. Navigate to Assignments > Device...
  3. From the Device Assignments window, click on the Device and Pin Options button.
  4. Under "Category", select General; and in the General sub-window, select the Configuration clock source from the available options.
  5. Under "Category", select Configuration; and in the Configuration sub-window, select the Active serial clock source from the available options. These options depend on what was selected in the previous step.

The value of the qspi_ref_clk is obtained by the bootloader when it takes ownership of the quad SPI Flash controller. The bootloader then typically passes this information to the end application or operating system.